View M65824AFP_178058.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Specifications
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC DESCRIPTION The M65824AFP is a CMOS IC developed for compact disc players. (suitable for CD-DA:Compact Disc-Digital Audio) It has built-in memory,adjustment-free PLL and D/A converter with DSP function. FEATURES Adjustment free EFM-PLL circuit(Includes VCO) 8 frames jitter margin Digital CLV servo control Attenuation(-12dB) 4 times over sampling IIR type digital filter Digital de-emphasis function D/A converter A smaller package Analog LPF Digital audio interface External D/A mode RECOMMENDED OPERATING CONDITIONS Supply voltage range(interface)*****************************************************************************DVDD=2.7 to 5.5V Supply voltage range(internal logic system and analog)**********************DSPS,AVDD=2.7 to 3.3V Rated supply voltage(interface)****************************************************************************************DVDD=5.0V Rated supply voltage(internal logic sys tem and analog)*********************************DSPS,AVDD=3.0V Rated power dissipation***********************************************************************************************************100mW SYSTEM BLOCK DIAGRAM
Subcode Interface
M65824AFP
Display Inter polation DeEMP
M
Motor Driver
Optical Pick-up
RF-Amp Pick-up Servo Auto
Adjustment
PLL Slicer
EFM De-modulator OSC CLK 18kSRAM
PLL CLK
CLV Digital Servo MCU I/F
ECC
C1:2error C2:2error
4fs Digital Filter
D/A
L R
System Control Microprocessor
MITSUBISHI ELECTRIC
1 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
1.BUILT-IN FUNCTIONS
Functional block D/A converter Memory PLL Description: * 64fs 1bit D/A converter * S/N:74dB(theoretically) * 18kSRAM(built-in) * 8 fames jitter margin * Adjustment free VCO * Slice level control * EFM demodulation * Frame sync.detection,protection&interpolation * Frame sync.signal output * Subcode P to W decoding,serial output * Subcode Q register * Subcode Q-CRC Check * Subcode sync.signal output(S0/S1) * Emphasis detection,built-in de-emphasis circuit control * C1:Duplex,C2:Duplex * De-scramble * De-interleave * Error monitor output * Averaging/Holding * Muting control * 4 times over sampling digital filter * Digital de-emphasis (IIR type digital filter) * Automatic emphasis flag detection * PWM output * Low disc rotation detection * CLV digital servo control * Muting control * Attenuation(-12dB) * Subcode Q register interface * Digital audio interface output ON/OFF * Clock accuracy input * TLC voltage "hold" * LPF output "open" * PWM output "regular acceleration"
EFM demodulator
Subcode decoding
CRC decoding
Data interpolator D/A interface Digital filter De-emphasis CLV digital servo
Microcomputer interface
Digital audio interface HFD
MITSUBISHI ELECTRIC
2 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
2. PIN CONFIGURATION
AVSS ADJCLK LOCK/DRD TEST I/O ACLRB
C423/DSCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
AVDD IREF
RAGND ROUT/LRCK RAVDD LAVDD LOUT/DO LAGND
DOTX XI DVSS XO TEST SBCO SCCK SYCLK EFFK KILLB EST1 EST2 HF TLC LPF
EXP2 EXP1 MLAB MSD MCK DVSS2 DVDD2 PWM SCAND CRCF SBQS DSPS DVDD
MITSUBISHI ELECTRIC
3 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
3. BLOCK DIAGRAM
MODULATOR AVSS ADJCLK LOCK/DRD TESTI/O ACLRB C423/DSCK DOTX XI DVSS XO TEST SBCO SCCK SYCLK EFFK KILLB EST1 EST2 HF TLC LPF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 HFD Generate 18 19 20 21 HF COMPARATOR VCO PHASE FREQ DET. DET. HFD CONTROL SUBCODE DEMOD SUBCODE Q CRC SUBCODE Q REGISTER VDD f or INTERNAL LOGIC DIGITAL VDD1 25 24 23 22 SYNC DET. EFM PROTECT DEMOD EFM TIMING GEN. . DIGITAL SILENCE DETECTOR DIGITAL GND2 DIGITAL VDD2 PWM MODULATOR TEST CONTROL X'tal TIMING GENERATOR CLOCK GENERATOR DIGITAL GND1 SEL TEST CONTROL RESET
DIGITAL AUDIO INTERFACE
ANALOG GND 3/4DETECTOR
Dither 16f s DIGITAL FILTER
1bitD/A LPF L/Rch
42 41
AVDD IREF RAGND ROUT/LRCK RAVDD LAVDD LOUT/D0 LAGND EXP2 EXP1 MLAB MSD MCK DVSS2 DVDD2 PWM SCAND CRCF SBQS DSPS DVDD
4f s DIGITAL FILTER DE-EMPHASIS FILTER INTERPOLATION MUTE CONTROL FREQ PHASE CONTROL CONTROL CLV SERVO CONTROL 18K SRAM (8bit x2400WORD MEMORY CONTROL CIRC DECODER ERROR MONITOR
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
MITSUBISHI ELECTRIC
4 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
4. PIN DESCRIPTION
pin No.
Name I/O Function
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
AVSS ADJCLK
LOCK/DRD
O O I I O O I O I O I O O O O O I O I/O -
Analog system GND Clock output for servo adjustment:f=88.2KHz Lock monitor / low disc rotation detect output Test control No pull-up System reset input : reset ="L" Crystal system clock output f=4.2336MHz Ext.D/A mode: Data shift clock output Digital out Crystal oscillator input (with Feedback R) f:8.4672MHz Digital system GND Crystal oscillator output Normal/Test select input : Test"H" Subcode serial output Shift clock input for subcode data read Frame lock status output : Lock="H" EFM frame clock output : duty=50% Digital silence : DIGITAL ZERO="L" Opendrain output Error status output 1 "H"When error detect at C1 decoder Error status output 1 "H"When error detect at C2 decoder High frequency signal input Slice level control signal output Loop filter for PLL Digital interface power supply Digital system power supply(internal logic)
MITSUBISHI ELECTRIC
TEST I/O ACLRB
C423/DSCK
DOTX XI DVSS XO TEST SBCO SCCK SYCLK EFFK KILLB EST1 EST2 HF TLC LPF DVDD DSPS
5 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
4.PIN DESCRIPTION(CONTINUANCE)
pin No.
Name I/O Function
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
SBQS CRCF SCAND PWM DVDD2 DVSS2 MCK MSD MLAB EXP1 EXP2 LAGND LOUT/D0 LAVDD RAVDD
ROUT/LRCK
O O O O I I/O I I I O O I -
Subcode Q register read interrupt signal "L" for read CRC checked results of Subcode Q:CRC OK="H" Subcode sync.signal output:"H" for sync. Disc motor driver PWM output(Both sides) Digital interface power supply2 Digital system GND2 Microcomputer interface shift clock input Microcomputer interface serial data I/O Microcomputer interface latch clock Built-in 22K pull up resistor to DVDD Input pin (be read via serial I/F) No.1 Built-in 4.7K pull up resistor to DVDD Input pin (be read via serial I/F) No.2 Built-in 4.7K pull up resistor to DVDD Lch Analog GND Audio signal output(L-ch) Ext.D/A mode;Audio serial data output Lch Analog power supply Rch Analog power supply Audio signal output(R-ch) Ext.D/A mode;LR clock output Rch Analog GND PLL circuit reference current setting Analog System power supply
RAGND IREF AVDD
Schmitt trigger input is the following ACLRB(No.5),TEST(No.11),SCCK(No.13),MCK(No.30) MLAB(No.32),EXP1(No.33),EXP2(No.34) Reset condition for ACLRB(No.5:No pull-up resistor,Normal CMOS input) minimum reset time :1sec
MITSUBISHI ELECTRIC
6 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
5.ABSOLUTE MAXIMUM RATINGS(Ta=25 ,unless otherwise noted) Symbol DVDD-DVSS AVDD-AVSS DSPS-DVSS Vi Vo Pd Topr Tstg Item Supply voltage(interface) Supply voltage(analog) Supply voltage(internal) Input voltage Output voltage Power dissipation Operating temperature Storage temperature Rating -0.3 to +6.5 -0.3 to +3.6 -0.3 to +3.6
DVSS-0.3 Vi DVDD+0.3
Unit V V V V V mV
DVSScVo DVDD 350 -10 to +70 -40 to +125
6.RECOM M ENDED OPERATING CONDITIONS Symbol DVDD AVDD DSPS VIH VIL fosc fvco Item
Supply voltage (interface) Supply voltage (analog) Supply voltage (internal) Input voltage ("H"level) Input voltage ("L"level) Output frequency Output frequency Except Schmitt input Except Schmitt input Normal speed Normal speed
conditions
Min
2.7 2.7 2.7
DVDDx 0.7
Typ
5.0 3.0 3.0 8.4672 8.4636
Max
5.5 3.3 3.3 DVDD
DVDDx 0.3
Unit
V V V V V MHz MHz
DVSS -
-
MITSUBISHI ELECTRIC
7 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
7.ELECTRICAL CHARACTERISTICS (Ta=25 ,DVDD=5V,AVDD/DSPS=3V unless otherwise noted)
Symbol IDD VOH VOL IIH IIL Ru VOH (DOTX) VOL (DOTX) Ileak (DOTX) Tf Tr Item Circuit current
Output voltage ("H"level) Output voltage ("L"level) Input current ("H"level) Input current ("L"level)
conditions
fosc=8.4672MHz fvco=8.6436MHz DVDD=5.0V IOH=-1.0mA DVDD=5.0V IOL=1.0mA
Min 4.5 -2
2.35 11
Typ 20.0 -
Max 0.4 2 9.4 44
Unit mA V V V V nsec nsec
VIH=4.5V VIL=0.5V
EXP1(33),EXP2(34) MLAB(32)
Pull up resistor output voltage ("H"level) output voltage ("L"level) output leakage current output (DOTX) fall time output (DOTX) rise time
DVDD=5.0V Ioh=-4.0mA DVDD=5.0V Iol=4.0mA DVDD=5V CL=20pF CL=20pF
4.6 -
-
0.4 10 10 10
8.D/A converter output (Ta=25 ,DVDD=5V,AVDD/DSPS=3V unless otherwise noted)
Symbol Vomax Freq THD SNR DR Item
Maximum output voltage Frequency characteristic
conditions
with System construction
with System construction (at 20KHz)
Min 1.8 72 72
Typ 2.0 -3.0 -
Max 2.2 0.2
-
Unit V dB %
dB dB
Distortion
Signal noise ratio
Dynamic range
20Hz to 20KHz (20KHz LPF)
20KHz LPF
A-weighted(20KHz LPF)
at-60dB(20KHz LPF) at 20KHz
72 -
-
-1.5
dB dB
Vgpass Passband ripple
MITSUBISHI ELECTRIC
8 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
9. POWER SUPPLY
2.7 to 3.3V 3.6 to 5.5V
M65824AFP
1 AVSS 9 DVSS 29 DVSS2 35 LAGND 40 RAGND DVDD2 28 DVDD 22 DSPS 23 LAVDD 37 RAVDD 38 AVDD 42
M65824AFP
1 AVSS 9 DVSS 29 DVSS2 35 LAGND 40 RAGND DVDD2 28 DVDD 22 DSPS 23 LAVDD 37 RAVDD 38 AVDD 42
2.7 to 3.3V
Fig.1 Application for 3.0V system
Fig.2 Application for 5.0V system
Fig.1 shows an application circuit for 3.0V system. Voltage range is between 2.7V to 3.3V. Fig.2 shows an application circuit for 5.0V system. The M65824AFP needs dual power supply. AVSS,DVSS,DVSS2,LAGND and RAGND should be connected to GND(0V). (Fig.1 and Fig.2)
10. FUNCTION DESCRIPTION
10-1 MICROCOMPUTER INTERFACE (1) Connection M65824AFP 31 CD-DA SIGNAL 30 PROCESSOR 32 MSD MCK MLAB I/O O O P
(2) Pin description MLAB:Microcomputer latch line for latching commands into the M65824AFP and for switching the communication mode. (MLAB=1:P writes to the M65824AFP) (MLAB=0:P reads from the M65824AFP)
MITSUBISHI ELECTRIC
9 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC MCK:Microcomputer clock line for clocking bits to or from the M65824AFP. MSD:Microcomputer data line for sending or receiving data bits from the M65824AFP. (3) Operation *Microcomputer command read/write operation The data bits (MSD) are accepted on the rising edge of the clock pulse(MCK).The falling edge of the latch line(MLAB) decides the complete command. At the same moment the data line is switched to output mode and indicates the status as requested by data bits D3,D2,D1 and D0. When the latch line becomes high,the data line is switched to input mode. *Status request / interface command If the microcomputer wants to read a certain status, it has to write a status request command with the appropriate bits D3,D2,D1 and D0 to the M65824AFP. After latching the command into the M65824AFP, the data line becomes the request status information as long as the latch line(MLAB) remains low. (4) Microcomputer I/O timing MSD
D0 D1 D2 D3 D4 D5 D6 D7 Status
MCK
t1 t2 t3 t4
MLAB
t5
t1:Shift clock width (min.200nsec) t2:Shift clock setup time (min.100nsec) t3:Shift clock hold time (min.100nsec) t4.Latch pulse setup time (min.100nsec) t5:Latch pulse width 50nsec t5 50s Subcode-Q reading:50nsec t5
MITSUBISHI ELECTRIC
10 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC (5) M65824AFP commands table Initial value after power on:00000000 D7 D6 Disc motor mode (6) Data description Reset condition
function Internal D/A mode , DOTX : OFF , Disc motor switched off , Audio muted , ACCK c lock level :
D5 D4 Audio function
D3 D2 D1 D0 Status Request/Interface command
Disc motor Mode D7 D6 Function
0 0 1 1
0 1 0 1
Disc motor switched off
Disc motor accelerate,applies maximum voltage for acceleration to the disc mo Disc motor brake,applies maximum voltage for braking to the disc motor
Disc motor CLV control mode
Function
Audio function D5 D4
0 0 1 1
D3 D2 D1
0 1 0 1
D0
Audio muted Audio mute off Prohibited Audio attenuate by 12dB
Function Disc rotation down status,Status="L" when disc motor speed <2/3 of nominal speed
Status request / Interface command
0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 1
0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1
PLL lock status,Status="L" when PLL is locked
Subcode ready status,Status="L" when new subcode has been receive
Status=Logical value of EXP1(Pin33) Status=Logical value of EXP1(Pin34) DOTX output DOTX off (high impedance) ACCK Clock accuracy input Level ACCK Clock accuracy input Level External D/A mode (IIS) External D/A mode (EIAJ) Internal D/A mode
MITSUBISHI ELECTRIC
11 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC (7) Subcode Q register interface The data of subcode Q stored in the internal 80-bit register can be read with a serial clock from the microcomputer. Procedure 1. THE microcomputer has to issue a subcode ready status command to the M65824AFP. Set MSD data "0100xxxx" and write to the M65824AFP. 2. If the status returned by the M65824AFP equals to subcode ready (status="L") then the microcomputer can read a subcode-Q data. 3. If the status is ready then the microcomputer starts clocking out the subcode-Q data from the M65824AFP with remaining the latch line "MLAB" status "L" as long as the microcomputer requires. 4. The microcomputer certainly sends 81 clocks. From the first clock to 80th clock read out subcode-Q data and 81th clock sets the status "H". 5. When the microcomputer finishes reading the subcode-Q data, (send 81 clocks) "MLAB" should be changed from "L" to "H". 6. If communication is aborted or doesn't finish normally,the M65824AFP and sends 81 clocks for initializing the internal 80-bit register and setting status "H". typ.136sec SBQS typ.13.3msec
MSD
B1 B2 B3 B4 B5 B6 B7 B8 B9 BA
MSD
Don't care Status Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 15 14 13
MCK t6 MLAB t6:Mode setup time(min.400nsec)
MITSUBISHI ELECTRIC
12 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
Description
Conditions under which the SBQS is placed in "L" (a) When the CRC checked results is good. (b) When both subcode sync signals S0 and S1 are detected in the specified position When both conditions (a) and (b) above are satisfied, the SBQS pin outputs "L". If SBQS does not turn to "L" then the subcode ready status indicates "H" (=not ready).When the subcode ready status is "H",the microcomputer can not read a valid subcode Q-channel data from the M65824AFP. The subcode-Q data is renewed at the same timing of the signal "SBQS" status is "L". When the microcomputer send a subcode ready status command,if the s ignal "MLAB" is changed from "H" to "L" during the signal "SBQS" status is "L" then the M65824AFP will return the status not ready. (status="H") While the latch line "MLAB" is remained "L", the subcode-Q data is not renewed. The M65824AFP output a subcode-Q data with reversed each 1-byte. (8)Subcode interface R-W The subcode data(P,Q,R,S,T,U,V,W) can be read from the SBCO pin by inputting clocks to the SCCK pin among the data converted from 14-bit EFM signal to 8-bit symbol. When both subcode sync. patterns S0,S1 are detected in the specified position as a sync. signal of this subcode, a sync. signal is output from SCAND pin. If 8 or more clocks are input to the SCCK, the SBCO is placed in "L". 10-2 DISCMOTORCONTROLPULSE(CLVMODE)
22.6757sec Min:0.2362sec Max:15.117sec
(DECELERATION)
PWM
(BOTH SIDES) (ACCELERATION)
Hi-Z Min:0.2362sec Max:15.117sec 22.6757sec
MITSUBISHI ELECTRIC
13 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
10-4. EFM - PLL circuit (1) Data slicing / PLL The M65824AFP has an analog front -end for incoming HF (EFM) signal. Using CMOS - Analog technology , the front - end is comprised of an automatic slice level control circuit and EFM - PLL circuit with internal adjust - free VCO. Under figure shows a block - diagram of the analog front - end. The HF signal is sliced by the HF comparator and a DC level is feed back from TLC to HF through some the external CR. If HFD becomes "H" because of defect in disk, then TLC becomes off state and holds the DC level. EFM -PLL is for extracting the EFM clock signal from the HF signal. The PLL circuit has a phase / frequency comparator so the M65824AFP has a wide capture / lock range and there is no need to adjust the VCO. LPF is the charge- pump output and same - time control voltage input to the VCO. LPF becomes off state if HFD becomes "H". IREF is the reference current input used to determine the current of charge pumps of TLC and LPF, operating point of HF comparator , and VCO free running frequency. If IREF is connected to a noisy power supply through a resistor , the VCO would be modulated and the error - rate would increase. Therefore , power supply noise at IREF must be held to a minimum.
TLC HF signal HF comparator changepump phase Det.
LPF
changepump
changepump
Vref
HFD
HF comparator 1/2 TLC Current source control LPF VCO Freq. Det Timer VCO Low freq limiter
IREF
EFM Data to EFM demodulator
EFM Clock
Async frame counter
Sync protection block
MITSUBISHI ELECTRIC
14 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC (2) Automatic slice level control CHF HF signal RTLC HF M65824AFP TLC CTLC
The slice level control circuit is formed by connecting a resistor and capacitors to the HF (High - frequency signal input ) pins. TLC(Slice level control output) pins. (Tentative Value) CHF=0.0010F CTLC=0.022F RTLC=33K Vin HF 0.5Vp-p min Since the adjustment - free VCO is built in, the adjustment - free PLL circuit can be formed by connecting a resistor and capacitors to the LPF (Low - pass filter) pin. (Tentative Value) CLPF=470pF C1=0.15F to 1.0F* RLPF=1.8K RPD=3.3M From 0.15F to 1.0F capacitor is available for C1. In high speed search such as track count search,the rotation of disc decrease. If this is problem, this problem is improved by using large C1. A resistor must be connected between the IREF pin and VDD in order to set the reference current used in determining the current values of the TLC pin and LPF pin , the comparator operating current of the slice level control circuit , and the VCO free - run frequency. (Tentative Value) RIREF=100K (Normal speed)
(3) PLL circuit LPF
RLPF
M65824AFP
RPD
CLPF C1
(4) Reference current
HF M65824AFP IREF
MITSUBISHI ELECTRIC
15 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
10-5.EFM demodulation The EFM signal that has been converted to logic level , and the EFM clock that has been extracted from the EFM signal are input to the demodulator and convert to 8bit symbol. The EFM demodulation depend on EFM table in the RED book. To demodulate , the demodulator must be synchronized to EFM signal for each frame. The frame sync.protection circuit holds the synchronization inspire of some lack of sync.pattern, and prevents false synchronization of the demodulator bit - slipping or mis - synchronization occurs. Frame sync.control block diagram show Fig.3.
EFM Symbol VCO
Edge dat.
23bit S/R
1/2
EFM timing generator /17 /35
Sync det.
/588 Reset Tfs Window generation
Sync
Sync. control
Lock state det. Window
HFD
Timer
Sync.frame counter
PLL control
Fig.3Frame sync.control block diagram
SYCLK
The generating condition of counter reset signal (Reset ) in the EFM timing generator is indicated as follows Reset = (Sync * Tfs ) + (Sync * Window) *:Logical product +:Logical sun Sync:Synchronizing signal Tfs:Detection signal of synchronizing signal space = 588 Window:Window signal 7ck In the synchronous state , Sync and Tfs generate simultaneously and Sync comes to the center of the window. At this time , "H" is output to the SYCLK pin , and EFM signal is synchronized by frame unit.
Content Frame lock Frame unlock
SYCLK L H
MITSUBISHI ELECTRIC
16 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC To monitor a sync.state with a control microcomputer,it is necessary to provide a signal from which a short-period missing of sync.pattern due to a disc defect,which occurs even in a sync.state is eliminated. In M65824AFP, this signal is allocated to LOCK/DRD pins.When the braking instruction from the microcomputer is not input, the LOCK/DRD pins monitor the sync.state in 1/16period of EFM frame clock, outputting the results; if monitored status is "locked" then output is "H" , continuous 8 times "unlocked " output becomes "L". And , when the disc rotation does not become the target speed , lock monitor may become "LOCK" state. In such state , some internal circuit does not work. So when the disc rotation become the target speed and change from rough servo mode to CLV mode , LOCK / DRD output lock monitor. LOCK/DRD pin outputs DRD signal when the disc motor is braking under the command from MCU.
Condition Not BRAKE status
Content Unlock by 1/16 frame clock Lock by 1/16 frame clock (Not CLV mode) Lock by 1/16 frame clock ( CLV mode)
LOCK/DRD L
H DRD signal
BRAKE status
Low disc rotation monitor signal
MITSUBISHI ELECTRIC
17 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC 10-6 Low disc rotary control When M65824AFP detects than the number of rotations is less than 2/3 that of the normal play state and the disc motor is braking under the command from MCU, it outputs the disc rotation deterioration signal to LOCK / DRD pin.
LOCK monitor LOCK/DRD
DRD
Less than 2/3 frequency
BRAKE Term Not BRAKE BRAKE Content Sync.status monitor output Disc rotation speed is more than 2/3 Disc rotation speed is less than 2/3 LOCK/DRD LOCK L H
MITSUBISHI ELECTRIC
18 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC 10-7. DIGITAL OUT
AUDIO DATA SHIFT REGISTER The digital audio signal formatted according to EIAJ PREAMBLE Standard CP-340 "Digital Audio Interface" is 16 outputted to DOTX pin. BIPHASE MARK DOTX SHIFT REGISTER The validity flag is internally set to "1" automatically MODULATION when the interpolated word is transmitted. The user data, which is read in the subcode CUV PARITY interface GENERATI Clock circuit,is transmitted. ON EST2 Channel clock precision can be set from the outside Accuracy CHANNEL SHIFT REGISTER TIMING STATUS so that it is compatible with the validity pitch. CIRCUIT The channel status is set to level in the validity 7 pitch,mode,and level is set automatically when it CONTROL SUBCODE Q TO W is not in the validity pitch mode. GENERATION OF
{
B:CHANNEL L AND TOP OF BLOCK M:CHANNEL L EXCEPT TOP OF BLOCK W:CHANNEL R
PARITY BIT CHANNEL STATUS USER DATA VALIDITY FLAG AUDIO DATA V U C P
SYNC
AUX
EXTENDED BIT
4 BIT
4 BIT
4 BIT
LSB
16 BIT
MSB
1
1
1
1
SUB frame format SUB FRAME SUB FRAME
M
L CHANNEL
W
R CHANNEL
B
L CHANNEL
W
R CHANNEL
M
L CHANNEL
FRAME 191 Frame format SOURCE CODING
FRAME 0
FRAME 1
Channel coding(Biphase mark modulation) If Digital-OUT is not used to prev ent spurious radiation, it is possible to turn DOTX pin output "OFF" by s etting mode command of microcomputer interf ace. Channel status clock precision can be set by ACCK command of m icrocomputer interf ace.
MITSUBISHI ELECTRIC
19 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
10-8.HFD
HFD is high frequency signal missing detect circuit. HFD is "ON" at HF signal missing. 1) TLC voltage "hold" 2) LPF output "open" 3) PWM output "regular acceleration" TLC voltage hold unit The block diagram for this TLC voltage hold unit is shown in Fig.4 below. This unit holds TLC voltage in stable condition and gives this voltage at HF signal missing. This unit holds two kinds of TLC voltage. By this method, this unit does not hold TLC voltage at HF signal missing and this unit can follow a difference of TLC voltage with the Disc.
HF Vref
Edge trigger circuit
HFD ON counter
HFD control circuit
HFD internal logic
HFD OFF counter
C423
TLC HOLD OFF counter
TLC HOLD control
TLC HOLD circuit
TLC
Fig.4 TLC voltage hold unit block diagram.
MITSUBISHI ELECTRIC
20 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC 10-9. Oscillation circuit (1)Internal oscillation mode The oscillation circuit can be formed by connecting a crystal oscillator(8.4672MHz)and load capacitors to pins XI and XO.
M65824AFP XI XO
C1
C2
Oscillator 8.4672MHz
load capacitor value(Reference) 30pF
MITSUBISHI ELECTRIC
21 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
MITSUBISHI ELECTRIC
22 /23
MITSUBISHI SOUND PROCESSOR ICs
M65824AFP
CD PLAYER DIGITAL SIGNAL PROCESSOR WITH BUILT-IN DAC
11. System construction
0.1u
1 2
AVSS
AVSS ADJCLK LOCK/DRD TEST I/O ACLRB C423/DSCK DOTX XI DVSS XO TEST SBCO SCCK SYCLK EFFK KILLB EST1 EST2 HF TLC LPF
AVDD IREF RAGND ROUT/LRCK RAVDD LAVDD LOUT/D0 LAGND EXP2 EXP1 MLAB MSD MCK DVSS2 DVDD2 PWM SCAND CRCF SBQS DSPS DVDD
42
100K
41 40 39 38 37 36 35 34 33 32 31 30
100p AVSS Audio L-CH Audio R-CH
3 4 5
DVSS
6 7
8.4672MHz 30p
0.1u
8 9 10
30p
11 12
DVSS
Microcomputer I/F
13 14
SUBCODE I/F
29 28 27 26 25 24 23 22
15 16 17
HF INPUT
Motor Driver
18
2200p
19
33K 470p 0.15u 1.8K 0.01u
20 21
AVSS DVSS
DVDD DSPS AVDD
MITSUBISHI ELECTRIC
23 /23

▲Up To Search▲

Price & Availability of M65824AFP

	To Download M65824AFP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .